(a) Field of the Invention
The present invention relates to a plasma display panel (PDP) and an apparatus and method for driving the same. More specifically, the present invention relates to an energy recovery circuit and a method for driving the same that directly contribute to plasma display discharge.
(b) Description of the Related Art
In recent years, flat panel displays such as liquid crystal displays (LCD), field emission displays (FED), PDPs, and the like have been actively developed. The PDP has advantages over the other flat panel displays because of its high luminance, high luminous efficiency, and wide view angle. Accordingly, the PDP is a preferred large-scale screen of larger than 40 inches that can substitute for the conventional display.
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. It includes, depending on its size, more than several scores to millions of pixels arranged in a matrix pattern. Such a PDP is classified as a direct current (DC) type or an alternating current (AC) type according to its discharge cell structure and the waveform of the driving voltage applied thereto.
The DC type PDP has electrodes exposed to a discharge space to allow DC to flow through the discharge space while the voltage is applied, and thus requires a resistance for limiting the current. To the contrary, the AC type PDP has electrodes covered with a dielectric layer that forms a capacitor to limit the current and protect the electrodes from the impact of ions during discharge. Thus, the AC type PDP has a longer lifetime than the DC type PDP.
FIG. 1 is a partial perspective view of an AC type PDP.
Referring to FIG. 1, on a first glass substrate 1 are arranged in parallel pairs of scan electrodes 4 and sustain electrodes 5 that are covered with a dielectric layer 2 and a protective layer 3. On a second glass substrate 6 are arranged a plurality of address electrodes 8 covered with an insulating layer 7. Barrier ribs 9 are formed in parallel with the address electrodes 8 on the insulating layer 7, which is interposed between the address electrodes 8. A fluorescent material 10 is formed on the surface of the insulating layer 7 and on both sides of the barrier ribs 9. The first and second glass substrates 1 and 6 are arranged face-to-face with a discharge space 11 formed therebetween, and the scan electrodes 4 and the sustain electrodes 5 lie normal to the address electrodes 8. The discharge space at the intersection between the address electrode 8 and the pair of scan electrode 4 and sustain electrode 5 forms a discharge cell 12.
FIG. 2 shows an arrangement of electrodes in the PDP.
Referring to FIG. 2, the PDP has a pixel matrix consisting of m×n discharge cells. In the PDP, address electrodes A1 to Am are arranged in columns and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are alternately arranged in rows. Discharge cells 12 shown in FIG. 2 correspond to the discharge cells 12 in FIG. 1.
Typically, the driving method of the AC type PDP is composed of a reset (initialization) step, a write (addressing) step, a sustain step, and an erase step.
In the reset step, the state of each cell is initialized to be ready for addressing the cell. In the write step, wall charges are applied in a selected cell that is on the panel (i.e., addressed cell). In the sustain step, a discharge occurs to actually display an image on the addressed cells. In the erase step, the wall charges on the cells are erased to finish the sustained discharge.
In the AC type PDP, the scan electrodes (hereinafter, referred to as “Y electrodes”) and the sustain electrodes (hereinafter, referred to as “X electrodes”) for the sustain discharge act as a capacitive load, so that there is a capacitance for the electrodes and a need for a reactive power as well as a power for a discharge. A circuit for recovering the reactive power and reusing it is called an “energy recovery circuit (or a sustain discharge circuit)”.
A conventional energy recovery circuit for the AC type PDP and its driving method are now described.
FIGS. 3 and 4 show a conventional energy recovery circuit and its waveform diagram, respectively.
FIG. 3 shows the energy recovery circuit disclosed in the U.S. Pat. Nos. 4,866,349 and 5,081,400 issued to L. F. Weber. The driver circuit for the AC type PDP includes an energy recovery circuit 30 of X electrodes that has the same configuration as an energy recovery circuit 31 (not shown) of Y electrodes. Expediently, the energy recovery circuit for one electrode will be described hereinafter.
The conventional energy recovery circuit 30 includes an energy recovery unit that comprises two switches Sa and Sb, diodes D1 and D2, an inductor Lc and an energy recovery capacitor Cc, and a sustain discharge unit that comprises two serially connected switches Sc and Sd.
A contact between the two switches Sc and Sd of the sustain discharge unit is coupled to the PDP, which is represented by a capacitor CP in an equivalent circuit.
The conventional energy recovery circuit as constructed above operates in four modes according to the states of the switches Sa to Sd, and shows the waveforms of output voltage VP and current IL flowing to the inductor LC, as illustrated in FIG. 4.
The switch Sd is initially ON before the switch Sa is turned ON, so that the terminal voltage VP of the panel is at zero. In the meantime, the energy recovery capacitor CC is already charged with a voltage (VS/2) that is half the sustain discharge voltage VS, lest an inrush current be generated at the start of a sustain discharge.
At t0, while the terminal voltage VP of the panel is maintained at zero, the mode 1 begins to turn the switch Sa ON and the switches Sb, Sc and Sd OFF.
In the operational interval (t0 to t1) of mode 1, an LC resonance path is formed in sequence of energy recovery capacitor CC, switch Sa, diode D1, inductor LC, and plasma panel capacitor CP. Accordingly, the current IL flowing to the inductor LC forms a half waveform because of LC resonance, and the output voltage VP of the panel gradually increases to the sustain discharge voltage VS. The moment that the output voltage VP of the panel reaches the sustain discharge voltage VS, almost no current flows to the inductor LC.
The mode 2 begins at the end of the mode 1, to turn the switches Sa and Sc ON and the switches Sb and Sd OFF. In the operational interval (t1 to t2) of mode 2, the sustain discharge voltage VS is applied to the panel capacitor CP via the switch Sc to maintain the output voltage VP of the panel. At t1, zero-voltage switching occurs because the terminal voltage of the switch Sc is ideally zero.
Once the mode 2 ends, the mode 3 begins to turn the switch Sb ON and the switches Sa, Sc and Sd OFF.
In the operational interval (t2 to t3) of mode 3, an LC resonance path is formed in reverse path of the LC resonance path in mode 1, i.e., a current path including plasma panel capacitor CP, inductor LC, diode D2, switch Sb, and energy recovery capacitor CC in sequence. Accordingly, as shown in FIG. 4, the current IL flows to the inductor LC and the output voltage VP of the panel falls, so that the current IL of the inductor LC and the output voltage VP of the panel reach zero at t3.
In the operational interval of mode 4, the switches Sb and Sd are turned ON and the switches Sa and Sc are OFF to maintain the output voltage VP of the panel at zero. Once the switch Sa is ON in this state, the cycle returns to mode 1.
Such a conventional energy recovery circuit, however, causes a problem because it is impossible to perform zero-voltage switching of the switches constituting the circuit due to the parasitic components of the actual circuit (e.g., the parasitic resistance of the inductor, the parasitic resistance of the capacitor and the panel, or resistance of the switches) with a consequence of a great switching loss while the switch is on. In other words, the magnetic energy stored in the inductor LC is ideally zero in the conventional energy recovery circuit when the voltage at one terminal of the panel capacitor is increased by the sustain discharge voltage VS. Thus, there is no source to raise the voltage at the terminal of the panel capacitor to VS, if the voltage at the one terminal of the panel capacitor does not reach VS due to the parasitic components of the actual circuit. Accordingly, the actual switch SC is not capable of zero-voltage switching to increase a switching loss when it is turned on.
Also, the energy recovery capacitor CC of the conventional energy recovery circuit has to be charged with VS/2 after starting discharge. Otherwise, a great inrush current is generated at the start of a sustain discharge pulse, which may require a protective circuit to reduce the inrush current.
Furthermore, a long period of rising/falling time of the panel voltage in the conventional energy recovery circuit may cause a discharge of the panel during the energy recovery interval (i.e., the rising/falling interval of the panel voltage). This may drop the panel voltage to cause a hard switching of the sustain switch SC and hence a great switching loss when the switch is turned on.